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MCP23017/MCP23S1716-Bit I/O Expander with Serial InterfaceFeaturesPackage Types� 16-bit remote bidirectional I/O portPDIP, GPB0...

何耀辉 Jessica

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何耀辉 Jessica · 2021-01-17 12:43:26 发布

MCP23017/MCP23S17

16-Bit I/O Expander with Serial Interface

Features Package Types

� 16-bit remote bidirectional I/O port PDIP, GPB0 �1 28 GPA7

- I/O pins default to input

SOIC, GPB1 2 27 GPA6

� High-speed I2CTM interface (MCP23017) SSOP GPB2 3

- 100 kHz GPB3 4 26 GPA5

- 400 kHz

- 1.7 MHz 25 GPA4

� High-speed SPI interface (MCP23S17) GPB4 5 MCP23017 24 GPA3

- 10 MHz (max.)

GPB5 6 23 GPA2

� Three hardware address pins to allow up to eight

devices on the bus GPB6 7 22 GPA1

� Configurable interrupt output pins GPB7 8 21 GPA0

- Configurable as active-high, active-low or

open-drain VDD 9 20 INTA

� INTA and INTB can be configured to operate VSS 10 19 INTB

independently or together

NC 11 18 RESET

� Configurable interrupt source

- Interrupt-on-change from configured register SCL 12 17 A2

defaults or pin changes

MCP23017 SDA 13 16 A1

� Polarity Inversion register to configure the polarity

of the input port data NC 14 15 A0

� External Reset input GPB3

� Low standby current: 1 �A (max.) GPB2

� Operating voltage: GPB1

GPB0

- 1.8V to 5.5V @ -40�C to +85�C GPA7

- 2.7V to 5.5V @ -40�C to +85�C GPA6

- 4.5V to 5.5V @ -40�C to +125�C GPA5

Packages QFN 28 2726 25242322

� 28-pin PDIP (300 mil) GPB4 1 21 GPA4

� 28-pin SOIC (300 mil) GPB5 GPA3

� 28-pin SSOP GPB6 2 20 GPA2

� 28-pin QFN GPB7 GPA1

3 19 GPA0

VDD INTA

VSS 4 MCP23017 18

NC INTB

5 17

6 16

7 15

8 9 10 11121314

SCL

SDA

RESET

PDIP, GPB0 �1 28 GPA7

SOIC, GPB1 2 27 GPA6

SSOP GPB2 3 26 GPA5

GPB3 4

25 GPA4

GPB4 5 MCP23S17 24 GPA3

GPB5 6 23 GPA2

GPB6 7 22 GPA1

GPB7 8 21 GPA0

VDD 9 20 INTA

VSS 10 19 INTB

CS 11 18 RESET

SCK 12 17 A2

MCP23S17 SI 13 16 A1

SO 14 15 A0

GPB3

GPB2

GPB1

GPB0

GPA7

GPA6

GPA5

QFN 28 2726 25242322

GPB4 1 21 GPA4

GPB5 GPA3

GPB6 2 20 GPA2

GPB7 GPA1

3 19 GPA0

VDD INTA

VSS 4 MCP23S17 18

CS INTB

5 17

6 16

7 15

8 9 10 11121314

SCK

RESET

� 2007 Microchip Technology Inc. DS21952B-page 1

MCP23017/MCP23S17

Functional Block Diagram

MCP23S17

CS SPI

SCK

MCP23017

SO I2CTM Serializer/ GPB7

Deserializer GPB6

SCL GPB5

SDA 3 Control GPIO GPB4

Decode 16 GPB3

A2:A0 GPB2

RESET Interrupt GPIO GPB1

Logic GPB0

INTA

INTB GPA7

GPA6

8 GPA5

GPA4

Configuration/ GPA3

Control GPA2

Registers GPA1

GPA0

DS21952B-page 2 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.0 DEVICE OVERVIEW There are two interrupt pins, INTA and INTB, that can

be associated with their respective ports, or can be

The MCP23017/MCP23S17 (MCP23X17) device logically OR'ed together so that both pins will activate if

family provides 16-bit, general purpose parallel I/O either port causes an interrupt.

expansion for I2C bus or SPI applications. The two

devices differ only in the serial interface. The interrupt output can be configured to activate

� MCP23017 � I2C interface under two conditions (mutually exclusive):

� MCP23S17 � SPI interface 1. When any input state differs from its

corresponding Input Port register state. This is

The MCP23X17 consists of multiple 8-bit configuration used to indicate to the system master that an

registers for input, output and polarity selection. The input state has changed.

system master can enable the I/Os as either inputs or

outputs by writing the I/O configuration bits (IODIRA/B). 2. When an input state differs from a preconfigured

The data for each input or output is kept in the register value (DEFVAL register).

corresponding input or output register. The polarity of

the Input Port register can be inverted with the Polarity The Interrupt Capture register captures port values at

Inversion register. All registers can be read by the the time of the interrupt, thereby saving the condition

system master. that caused the interrupt.

The 16-bit I/O port functionally consists of two 8-bit The Power-on Reset (POR) sets the registers to their

ports (PORTA and PORTB). The MCP23X17 can be default values and initializes the device state machine.

configured to operate in the 8-bit or 16-bit modes via

IOCON.BANK. The hardware address pins are used to determine the

device address.

� 2007 Microchip Technology Inc. DS21952B-page 3

MCP23017/MCP23S17

1.1 Pin Descriptions

TABLE 1-1: PINOUT DESCRIPTION

Pin PDIP/ QFN Pin Function

Name SOIC/ Type

SSOP

GPB0 1 25 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPB1 2 26 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPB2 3 27 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPB3 4 28 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPB4 5 1 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPB5 6 2 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPB6 7 3 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPB7 8 4 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

VDD 9 5 P Power

VSS

NC/CS 10 6 P Ground

11 7 I NC (MCP23017), Chip Select (MCP23S17)

SCL/SCK 12 8 I Serial clock input

SDA/SI 13 9 I/O Serial data I/O (MCP23017), Serial data input (MCP23S17)

NC/SO 14 10 O NC (MCP23017), Serial data out (MCP23S17)

A0 15 11 I Hardware address pin. Must be externally biased.

A1 16 12 I Hardware address pin. Must be externally biased.

A2 17 13 I Hardware address pin. Must be externally biased.

RESET 18 14 I Hardware reset. Must be externally biased.

INTB 19 15 O Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.

INTA 20 16 O Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.

GPA0 21 17 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPA1 22 18 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPA2 23 19 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPA3 24 20 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPA4 25 21 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPA5 26 22 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPA6 27 23 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPA7 28 24 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

DS21952B-page 4 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.2 Power-on Reset (POR) 1.3.1 BYTE MODE AND SEQUENTIAL

MODE

The on-chip POR circuit holds the device in reset until

VDD has reached a high enough voltage to deactivate The MCP23X17 family has the ability to operate in Byte

the POR circuit (i.e., release the device from reset). mode or Sequential mode (IOCON.SEQOP).

The maximum VDD rise time is specified in Section 2.0

"Electrical Characteristics". Byte Mode disables automatic Address Pointer

incrementing. When operating in Byte mode, the

When the device exits the POR condition (releases MCP23X17 family does not increment its internal

reset), device operating parameters (i.e., voltage, address counter after each byte during the data

temperature, serial bus frequency, etc.) must be met to transfer. This gives the ability to continually access the

ensure proper operation. same address by providing extra clocks (without

additional control bytes). This is useful for polling the

1.3 Serial Interface GPIO register for data changes or for continually

writing to the output latches.

This block handles the functionality of the I2C

(MCP23017) or SPI (MCP23S17) interface protocol. A special mode (Byte mode with IOCON.BANK = 0)

The MCP23X17 contains 22 individual registers (11 causes the address pointer to toggle between

Interface block, as shown in Table 1-2. bit is cleared and the Address Pointer is initially set to

address 12h (GPIOA) or 13h (GPIOB), the pointer will

TABLE 1-2: REGISTER ADDRESSES toggle between GPIOA and GPIOB. Note that the

Address Pointer can initially point to either address in

Address Address Access to: the register pair.

IOCON.BANK = 1 IOCON.BANK = 0

Sequential mode enables automatic address pointer

00h 00h IODIRA incrementing. When operating in Sequential mode, the

MCP23X17 family increments its address counter after

10h 01h IODIRB each byte during the data transfer. The Address Pointer

automatically rolls over to address 00h after accessing

01h 02h IPOLA the last register.

11h 03h IPOLB

02h 04h GPINTENA These two modes are not to be confused with single

writes/reads and continuous writes/reads that are

12h 05h GPINTENB serial protocol sequences. For example, the device

may be configured for Byte mode and the master may

03h 06h DEFVALA perform a continuous read. In this case, the

MCP23X17 would not increment the Address Pointer

13h 07h DEFVALB and would repeatedly drive data from the same

location.

04h 08h INTCONA

14h 09h INTCONB

05h 0Ah IOCON

15h 0Bh IOCON

06h 0Ch GPPUA 1.3.2 I2C INTERFACE

16h 0Dh GPPUB 1.3.2.1 I2C Write Operation

07h 0Eh INTFA The I2C write operation includes the control byte and

17h 0Fh INTFB Figure 1-1. This sequence is followed by eight bits of

data from the master and an Acknowledge (ACK) from

08h 10h INTCAPA the MCP23017. The operation is ended with a Stop (P)

or Restart (SR) condition being generated by the

18h 11h INTCAPB master.

09h 12h GPIOA Data is written to the MCP23017 after every byte

transfer. If a Stop or Restart condition is generated

19h 13h GPIOB during a data transfer, the data will not be written to the

MCP23017.

0Ah 14h OLATA

Both "byte writes" and "sequential writes" are

1Ah 15h OLATB supported by the MCP23017. If Sequential mode is

enabled (IOCON, SEQOP = 0) (default), the

MCP23017 increments its address counter after each

ACK during the data transfer.

� 2007 Microchip Technology Inc. DS21952B-page 5

MCP23017/MCP23S17

1.3.2.2 I2C Read Operation 1.3.3 SPI INTERFACE

I2C Read operations include the control byte sequence,

as shown in the bottom of Figure 1-1. This sequence is 1.3.3.1 SPI Write Operation

followed by another control byte (including the Start

condition and ACK) with the R/W bit set (R/W = 1). The The SPI write operation is started by lowering CS. The

MCP23017 then transmits the data contained in the Write command (slave address with R/W bit cleared) is

addressed register. The sequence is ended with the then clocked into the device. The opcode is followed by

master generating a Stop or Restart condition. an address and at least one data byte.

1.3.2.3 I2C Sequential Write/Read 1.3.3.2 SPI Read Operation

For sequential operations (Write or Read), instead of The SPI read operation is started by lowering CS. The

transmitting a Stop or Restart condition after the data SPI read command (slave address with R/W bit set) is

transfer, the master clocks the next byte pointed to by then clocked into the device. The opcode is followed by

the address pointer (see Section 1.3.1 "Byte Mode an address, with at least one data byte being clocked

and Sequential Mode" for details regarding sequential out of the device.

operation control).

1.3.3.3 SPI Sequential Write/Read

The sequence ends with the master sending a Stop or

Restart condition. For sequential operations, instead of deselecting the

device by raising CS, the master clocks the next byte

The MCP23017 Address Pointer will roll over to pointed to by the Address Pointer. (see Section 1.3.1

address zero after reaching the last register address. "Byte Mode and Sequential Mode" for details

regarding sequential operation control).

Refer to Figure 1-1.

The sequence ends by the raising of CS.

The MCP23S17 Address Pointer will roll over to

address zero after reaching the last register address.

DS21952B-page 6 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

FIGURE 1-1: MCP23017 I2CTM DEVICE PROTOCOL

S - Start

SR - Restart S OP W ADDR DIN .... DIN P

P - Stop

w - Write SR OP R DOUT .... DOUT P

R - Read

OP - Device opcode SR OP W DIN .... DIN P

ADDR - Device register address P

DOUT - Data out from MCP23017

DIN - Data in to MCP23017

S OP R DOUT .... DOUT P

SR OP R DOUT .... DOUT P

SR OP W ADDR DIN .... DIN P

Byte and Sequential Write

Byte S OP W ADDR DIN P

Sequential S OP W ADDR DIN .... DIN P

Byte and Sequential Read

Byte S OP W SR OP R DOUT P

Sequential S OP W SR OP R DOUT .... DOUT P

� 2007 Microchip Technology Inc. DS21952B-page 7

MCP23017/MCP23S17

1.4 Hardware Address Decoder FIGURE 1-2: I2CTM CONTROL BYTE

FORMAT

The hardware address pins are used to determine the

device address. To address a device, the correspond- Control Byte

ing address bits in the control byte must match the pin S 0 1 0 0 A2 A1 A0 R/W ACK

state. The pins must be biased externally.

1.4.1 ADDRESSING I2C DEVICES Slave Address

(MCP23017)

Start R/W bit

The MCP23017 is a slave I2C interface device that bit ACK bit

supports 7-bit slave addressing, with the read/write bit

filling out the control byte. The slave address contains R/W = 0 = write

four fixed bits and three user-defined hardware R/W = 1 = read

address bits (pins A2, A1 and A0). Figure 1-2 shows

the control byte format. FIGURE 1-3: SPI CONTROL BYTE

FORMAT

1.4.2 ADDRESSING SPI DEVICES

(MCP23S17)

The MCP23S17 is a slave SPI device. The slave Control Byte

address contains four fixed bits and three user-defined 0 1 0 0 A2 A1 A0 R/W

hardware address bits (if enabled via IOCON.HAEN)

(pins A2, A1 and A0) with the read/write bit filling out Slave Address

the control byte. Figure 1-3 shows the control byte

format. The address pins should be externally biased R/W bit

even if disabled (IOCON.HAEN = 0).

R/W = 0 = write

R/W = 1 = read

FIGURE 1-4: I2CTM ADDRESSING REGISTERS

S 0 1 0 0 A2 A1 A0 0 ACK* A7 A6 A5 A4 A3 A2 A1 A0 ACK*

R/W = 0

Device Opcode Register Address

*The ACKs are provided by the MCP23017.

FIGURE 1-5: SPI ADDRESSING REGISTERS

0 1 0 0 A2 A1 A0 R/W A7 A6 A5 A4 A3 A2 A1 A0

***

Device Opcode Register Address

* Address pins are enabled/disabled via IOCON.HAEN.

DS21952B-page 8 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.5 GPIO Port Reading the GPIOn register reads the value on the

port. Reading the OLATn register only reads the

The GPIO module is a general purpose, 16-bit wide, latches, not the actual value on the port.

bidirectional port that is functionally split into two 8-bit

wide ports. Writing to the GPIOn register actually causes a write to

the latches (OLATn). Writing to the OLATn register

The GPIO module contains the data ports (GPIOn), forces the associated output drivers to drive to the level

internal pull-up resistors and the output latches in OLATn. Pins configured as inputs turn off the

(OLATn). associated output driver and put it in high-impedance.

TABLE 1-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1)

value

Name (hex)

IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111

IPOLA

GPINTENA 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000

GPPUA

GPIOA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000

OLATA

IODIRB 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000

IPOLB

GPINTENB 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000

GPPUB

GPIOB 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000

OLATB

10 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111

11 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000

12 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000

16 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000

19 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000

1A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000

TABLE 1-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 0)

value

Name (hex)

IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111

IODIRB

IPOLA 01 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111

IPOLB

GPINTENA 02 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000

GPINTENB

GPPUA 03 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000

GPPUB

GPIOA 04 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000

GPIOB

OLATA 05 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000

OLATB

0C PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000

0D PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000

12 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000

13 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000

14 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000

15 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000

� 2007 Microchip Technology Inc. DS21952B-page 9

MCP23017/MCP23S17

1.6 Configuration and Control are associated with PortB. One register (IOCON) is

Registers shared between the two ports. The PortA registers are

identical to the PortB registers, therefore, they will be

There are 21 registers associated with the MCP23X17, referred to without differentiating between the port

as shown in Table 1-5 and Table 1-6. The two tables designation (i.e., they will not have the "A" or "B"

show the register mapping with the two BANK bit designator assigned) in the register tables.

values. Ten registers are associated with PortA and ten

TABLE 1-5: CONTROL REGISTER SUMMARY (IOCON.BANK = 1)

value

Name (hex) IO1

IP1

IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 GPINT1 IO0 1111 1111

IPOLA DEF1 IP0 0000 0000

GPINTENA 01 IP7 IP6 IP5 IP4 IP3 IP2 IOC1 GPINT0 0000 0000

DEFVALA INTPOL DEF0 0000 0000

INTCONA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 PU1 IOC0 0000 0000

IOCON INT1 -- 0000 0000

GPPUA 03 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 ICP1 PU0 0000 0000

INTFA GP1 INTO 0000 0000

INTCAPA 04 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 OL1 ICP0 0000 0000

GPIOA IO1 GP0 0000 0000

OLATA 05 BANK MIRROR SEQOP DISSLW HAEN ODR IP1 OL0 0000 0000

IODIRB GPINT1 IO0 1111 1111

IPOLB 06 PU7 PU6 PU5 PU4 PU3 PU2 DEF1 IP0 0000 0000

GPINTENB IOC1 GPINT0 0000 0000

DEFVALB 07 INT7 INT6 INT5 INT4 INT3 INT2 INTPOL DEF0 0000 0000

INTCONB PU1 IOC0 0000 0000

IOCON 08 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 INT1 -- 0000 0000

GPPUB ICP1 PU0 0000 0000

INTFB 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 INTO 0000 0000

INTCAPB OL1 ICP0 0000 0000

GPIOB 0A OL7 OL6 OL5 OL4 OL3 OL2 GP0 0000 0000

OLATB OL0 0000 0000

10 IO7 IO6 IO5 IO4 IO3 IO2

11 IP7 IP6 IP5 IP4 IP3 IP2

12 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2

13 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2

14 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2

15 BANK MIRROR SEQOP DISSLW HAEN ODR

16 PU7 PU6 PU5 PU4 PU3 PU2

17 INT7 INT6 INT5 INT4 INT3 INT2

18 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2

19 GP7 GP6 GP5 GP4 GP3 GP2

1A OL7 OL6 OL5 OL4 OL3 OL2

DS21952B-page 10 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

TABLE 1-6: CONTROL REGISTER SUMMARY (IOCON.BANK = 0)

value

Name (hex) IO1

IO1

IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IP1 IO0 1111 1111

IODIRB IP1 IO0 1111 1111

IPOLA 01 IO7 IO6 IO5 IO4 IO3 IO2 GPINT1 IP0 0000 0000

IPOLB GPINT1 IP0 0000 0000

GPINTENA 02 IP7 IP6 IP5 IP4 IP3 IP2 DEF1 GPINT0 0000 0000

GPINTENB DEF1 GPINT0 0000 0000

DEFVALA 03 IP7 IP6 IP5 IP4 IP3 IP2 IOC1 DEF0 0000 0000

DEFVALB IOC1 DEF0 0000 0000

INTCONA 04 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 INTPOL IOC0 0000 0000

INTCONB INTPOL IOC0 0000 0000

IOCON 05 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 PU1 -- 0000 0000

IOCON PU1 -- 0000 0000

GPPUA 06 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 INT1 PU0 0000 0000

GPPUB INT1 PU0 0000 0000

INTFA 07 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 ICP1 INTO 0000 0000

INTFB ICP1 INTO 0000 0000

INTCAPA 08 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 GP1 ICP0 0000 0000

INTCAPB GP1 ICP0 0000 0000

GPIOA 09 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 OL1 GP0 0000 0000

GPIOB OL1 GP0 0000 0000

OLATA 0A BANK MIRROR SEQOP DISSLW HAEN ODR OL0 0000 0000

OLATB OL0 0000 0000

0B BANK MIRROR SEQOP DISSLW HAEN ODR

0C PU7 PU6 PU5 PU4 PU3 PU2

0D PU7 PU6 PU5 PU4 PU3 PU2

0E INT7 INT6 INT5 INT4 INT3 INT2

0F INT7 INT6 INT5 INT4 INT3 INT2

10 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2

11 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2

12 GP7 GP6 GP5 GP4 GP3 GP2

13 GP7 GP6 GP5 GP4 GP3 GP2

14 OL7 OL6 OL5 OL4 OL3 OL2

15 OL7 OL6 OL5 OL4 OL3 OL2

� 2007 Microchip Technology Inc. DS21952B-page 11

MCP23017/MCP23S17

1.6.1 I/O DIRECTION REGISTER

Controls the direction of the data I/O.

When a bit is set, the corresponding pin becomes an

input. When a bit is clear, the corresponding pin

becomes an output.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

bit 0

bit 7

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7-0 IO7:IO0: These bits control the direction of data I/O

1 = Pin is configured as an input.

0 = Pin is configured as an output.

DS21952B-page 12 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.6.2 INPUT POLARITY REGISTER

This register allows the user to configure the polarity on

the corresponding GPIO port bits.

If a bit is set, the corresponding GPIO register bit will

reflect the inverted value on the pin.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0

bit 0

bit 7

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7-0 IP7:IP0: These bits control the polarity inversion of the input pins

1 = GPIO register bit will reflect the opposite logic state of the input pin.

0 = GPIO register bit will reflect the same logic state of the input pin.

� 2007 Microchip Technology Inc. DS21952B-page 13

MCP23017/MCP23S17

1.6.3 INTERRUPT-ON-CHANGE

CONTROL REGISTER

The GPINTEN register controls the interrupt-on-

change feature for each pin.

If a bit is set, the corresponding pin is enabled for

interrupt-on-change. The DEFVAL and INTCON

registers must also be configured if any pins are

enabled for interrupt-on-change.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0

bit 7

bit 0

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7-0 GPINT7:GPINT0: General purpose I/O interrupt-on-change bits

1 = Enable GPIO input pin for interrupt-on-change event.

0 = Disable GPIO input pin for interrupt-on-change event.

Refer to INTCON and GPINTEN.

DS21952B-page 14 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.6.4 DEFAULT COMPARE REGISTER

FOR INTERRUPT-ON-CHANGE

The default comparison value is configured in the

DEFVAL register. If enabled (via GPINTEN and

INTCON) to compare against the DEFVAL register, an

opposite value on the associated pin will cause an

interrupt to occur.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0

bit 7

bit 0

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7-0 DEF7:DEF0: These bits set the compare value for pins configured for interrupt-on-change from

defaults . Refer to INTCON.

If the associated pin level is the opposite from the register bit, an interrupt occurs.

Refer to INTCON and GPINTEN.

� 2007 Microchip Technology Inc. DS21952B-page 15

MCP23017/MCP23S17

1.6.5 INTERRUPT CONTROL REGISTER

The INTCON register controls how the associated pin

value is compared for the interrupt-on-change feature.

If a bit is set, the corresponding I/O pin is compared

against the associated bit in the DEFVAL register. If a

bit value is clear, the corresponding I/O pin is compared

against the previous value.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0

bit 7

bit 0

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7-0 IOC7:IOC0: These bits control how the associated pin value is compared for interrupt-on-change

1 = Controls how the associated pin value is compared for interrupt-on-change.

0 = Pin value is compared against the previous pin value.

Refer to INTCON and GPINTEN.

DS21952B-page 16 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.6.6 CONFIGURATION REGISTER The MIRROR bit controls how the INTA and INTB pins

function with respect to each other.

The IOCON register contains several bits for

configuring the device: � When MIRROR = 1, the INTn pins are functionally

OR'ed so that an interrupt on either port will cause

The BANK bit changes how the registers are mapped both pins to activate.

(see Table 1-5 and Table 1-6 for more details).

� When MIRROR = 0, the INT pins are separated.

� If BANK = 1, the registers associated with each Interrupt conditions on a port will cause its

port are segregated. Registers associated with respective INT pin to activate.

PORTA are mapped from address 00h - 0Ah and

registers associated with PORTB are mapped The Sequential Operation (SEQOP) controls the

from 10h - 1Ah. incrementing function of the Address Pointer. If the

address pointer is disabled, the Address Pointer does

� If BANK = 0, the A/B registers are paired. For not automatically increment after each byte is clocked

example, IODIRA is mapped to address 00h and during a serial transfer. This feature is useful when it is

IODIRB is mapped to the next address (address desired to continuously poll (read) or modify (write) a

01h). The mapping for all registers is from 00h - register.

15h.

The Slew Rate (DISSLW) bit controls the slew rate

It is important to take care when changing the BANK bit function on the SDA pin. If enabled, the SDA slew rate

as the address mapping changes after the byte is will be controlled when driving from a high to low.

clocked into the device. The address pointer may point

to an invalid location after the bit is modified. The Hardware Address Enable (HAEN) bit enables/

disables hardware addressing on the MCP23S17 only.

For example, if the device is configured to The address pins (A2, A1 and A0) must be externally

automatically increment its internal Address Pointer, biased, regardless of the HAEN bit value.

the following scenario would occur:

If enabled (HAEN = 1), the device's hardware address

� BANK = 0 matches the address pins.

� Write 80h to address 0Ah (IOCON) to set the

If disabled (HAEN = 0), the device's hardware address

BANK bit is A2 = A1 = A0 = 0.

� Once the write completes, the internal address The Open-Drain (ODR) control bit enables/disables the

now points to 0Bh which is an invalid address INT pin for open-drain configuration. Erasing this bit

when the BANK bit is set. overrides the INTPOL bit.

For this reason, it is advised to only perform byte writes The Interrupt Polarity (INTPOL) sets the polarity of the

to this register when changing the BANK bit. INT pin. This bit is functional only when the ODR bit is

cleared, configuring the INT pin as active push-pull.

� 2007 Microchip Technology Inc. DS21952B-page 17

MCP23017/MCP23S17

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL --

bit 7

bit 0

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7 BANK: Controls how the registers are addressed

1 = The registers associated with each port are separated into different banks

0 = The registers are in the same bank (addresses are sequential)

bit 6 MIRROR: INT Pins Mirror bit

1 = The INT pins are internally connected

0 = The INT pins are not connected. INTA is associated with PortA and INTB is associated with PortB

bit 5 SEQOP: Sequential Operation mode bit.

1 = Sequential operation disabled, address pointer does not increment.

0 = Sequential operation enabled, address pointer increments.

bit 4 DISSLW: Slew Rate control bit for SDA output.

1 = Slew rate disabled.

0 = Slew rate enabled.

bit 3 HAEN: Hardware Address Enable bit (MCP23S17 only).

Address pins are always enabled on MCP23017.

1 = Enables the MCP23S17 address pins.

0 = Disables the MCP23S17 address pins.

bit 2 ODR: This bit configures the INT pin as an open-drain output.

1 = Open-drain output (overrides the INTPOL bit).

0 = Active driver output (INTPOL bit sets the polarity).

bit 1 INTPOL: This bit sets the polarity of the INT output pin.

1 = Active-high.

0 = Active-low.

bit 0 Unimplemented: Read as `0'.

DS21952B-page 18 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.6.7 PULL-UP RESISTOR

CONFIGURATION REGISTER

The GPPU register controls the pull-up resistors for the

port pins. If a bit is set and the corresponding pin is

configured as an input, the corresponding port pin is

internally pulled up with a 100 k resistor.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0

bit 7

bit 0

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7-0 PU7:PU0: These bits control the weak pull-up resistors on each pin (when configured as an input)

1 = Pull-up enabled.

0 = Pull-up disabled.

� 2007 Microchip Technology Inc. DS21952B-page 19

MCP23017/MCP23S17

1.6.8 INTERRUPT FLAG REGISTER

The INTF register reflects the interrupt condition on the

port pins of any pin that is enabled for interrupts via the

GPINTEN register. A `set' bit indicates that the

associated pin caused the interrupt.

This register is `read-only'. Writes to this register will be

ignored.

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0

bit 7

bit 0

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7-0 INT7:INT0: These bits reflect the interrupt condition on the port. Will reflect the change only if interrupts

are enabled (GPINTEN) .

1 = Pin caused interrupt.

0 = Interrupt not pending.

DS21952B-page 20 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.6.9 INTERRUPT CAPTURE REGISTER

The INTCAP register captures the GPIO port value at

the time the interrupt occurred. The register is `read

only' and is updated only when an interrupt occurs. The

cleared via a read of INTCAP or GPIO.

R-x R-x R-x R-x R-x R-x R-x R-x

ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0

bit 7

bit 0

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7-0 ICP7:ICP0: These bits reflect the logic level on the port pins at the time of interrupt due to pin change

1 = Logic-high.

0 = Logic-low.

� 2007 Microchip Technology Inc. DS21952B-page 21

MCP23017/MCP23S17

1.6.10 PORT REGISTER

The GPIO register reflects the value on the port.

Reading from this register reads the port. Writing to this

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0

bit 7

bit 0

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7-0 GP7:GP0: These bits reflect the logic level on the pins

1 = Logic-high.

0 = Logic-low.

DS21952B-page 22 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.6.11 OUTPUT LATCH REGISTER (OLAT)

The OLAT register provides access to the output

latches. A read from this register results in a read of the

OLAT and not the port itself. A write to this register

modifies the output latches that modifies the pins

configured as outputs.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0

bit 7

bit 0

Legend: W = Writable bit U = Unimplemented bit, read as `0'

R = Readable bit `1' = Bit is set

-n = Value at POR `0' = Bit is cleared x = Bit is unknown

bit 7-0 OL7:OL0: These bits reflect the logic level on the output latch

1 = Logic-high.

0 = Logic-low.

� 2007 Microchip Technology Inc. DS21952B-page 23

MCP23017/MCP23S17

1.7 Interrupt Logic 1.7.2 IOC FROM PIN CHANGE

If enabled, the MCP23X17 activates the INTn interrupt If enabled, the MCP23X17 will generate an interrupt if

output when one of the port pins changes state or when a mismatch condition exists between the current port

a pin does not match the preconfigured default. Each value and the previous port value. Only IOC enabled

pin is individually configurable as follows: pins will be compared. Refer to Register 1-3 and

� Enable/disable interrupt via GPINTEN

� Can interrupt on either pin change or change from 1.7.3 IOC FROM REGISTER DEFAULT

default as configured in DEFVAL If enabled, the MCP23X17 will generate an interrupt if

a mismatch occurs between the DEFVAL register and

Both conditions are referred to as Interrupt-on-Change the port. Only IOC enabled pins will be compared.

(IOC). Refer to Register 1-3, Register 1-5 and Register 1-4.

The interrupt control module uses the following 1.7.4 INTERRUPT OPERATION

registers/bits:

The INTn interrupt output can be configured as active-

� IOCON.MIRROR � controls if the two interrupt low, active-high or open-drain via the IOCON register.

pins mirror each other

Only those pins that are configured as an input (IODIR

� GPINTEN � Interrupt enable register register) with Interrupt-On-Change (IOC) enabled

� INTCON � Controls the source for the IOC (IOINTEN register) can cause an interrupt. Pins

� DEFVAL � Contains the register default for IOC defined as an output have no effect on the interrupt

output pin.

operation

Input change activity on a port input pin that is enabled

1.7.1 INTA AND INTB for IOC will generate an internal device interrupt and

the device will capture the value of the port and copy it

There are two interrupt pins: INTA and INTB. By into INTCAP. The interrupt will remain active until the

default, INTA is associated with GPAn pins (PortA) and INTCAP or GPIO register is read. Writing to these

INTB is associated with GPBn pins (PortB). Each port registers will not affect the interrupt. The interrupt

has an independent signal which is cleared if its condition will be cleared after the LSb of the data is

associated GPIO or INTCAP register is read. clocked out during a read command of GPIO or

INTCAP.

1.7.1.1 Mirroring the INT pins

The first interrupt event will cause the port contents to

Additionally, the INTn pins can be configured to mirror be copied into the INTCAP register. Subsequent

each other so that any interrupt will cause both pins to interrupt conditions on the port will not cause an

go active. This is controlled via IOCON.MIRROR. interrupt to occur as long as the interrupt is not cleared

by a read of INTCAP or GPIO.

If IOCON.MIRROR = 0, the internal signals are routed

independently to the INTA and INTB pads. Note: The value in INTCAP can be lost if GPIO is

read before INTCAP while another IOC is

If IOCON.MIRROR = 1, the internal signals are OR'ed pending. After reading GPIO, the interrupt

together and routed to the INTn pads. In this case, the will clear and then set due to the pending

interrupt will only be cleared if the associated GPIO or IOC, causing the INTCAP register to

INTCAP is read (see Table 1-7). update.

TABLE 1-7: INTERRUPT OPERATION

(IOCON.MIRROR = 1)

Interrupt Read Portn * Interupt Result

Condition

GPIOA PortA Clear

GPIOB PortB Unchanged

PortA Unchanged

PortB

PortA Clear

Unchanged

GPIOA and PortB Unchanged

GPIOB Clear

Both PortA and

PortB

* Port n = GPIOn or INTCAPn

DS21952B-page 24 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.7.5 INTERRUPT CONDITIONS FIGURE 1-7: INTERRUPT-ON-CHANGE

FROM REGISTER

There are two possible configurations that cause DEFAULT

interrupts (configured via INTCON):

DEFVAL REGISTER

1. Pins configured for interrupt-on-pin change GP: 7 6 5 4 3 2 1 0

will cause an interrupt to occur if a pin changes

to the opposite state. The default state is reset XXXXX0 XX

after an interrupt occurs and after clearing the

interrupt condition (i.e., after reading GPIO or GP2

INTCAP). For example, an interrupt occurs by Pin

an input changing from `1' to `0'. The new initial

state for the pin is a logic 0 after the interrupt is INT ACTIVE ACTIVE

cleared.

2. Pins configured for interrupt-on-change from

the corresponding input pin differs from the is captured or INTCAP

long as the condition exists, regardless if the (INT clears only if interrupt

INTCAP or GPIO is read. condition does not exist.)

See Figure 1-6 and Figure 1-7 for more information on

interrupt operations.

FIGURE 1-6: INTERRUPT-ON-PIN

CHANGE

GPx

INT ACTIVE ACTIVE

Port value Read GPIO Port value

is captured or INTCAP is captured

into INTCAP

� 2007 Microchip Technology Inc. DS21952B-page 25

MCP23017/MCP23S17

NOTES:

DS21952B-page 26 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

2.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Ambient temperature under bias............................................................................................................. -40�C to +125�C

Storage temperature ............................................................................................................................... -65�C to +150�C

Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +5.5V

Voltage on all other pins with respect to VSS (except VDD)............................................................. -0.6V to (VDD + 0.6V)

Total power dissipation (Note) .............................................................................................................................700 mW

Maximum current out of VSS pin ...........................................................................................................................150 mA

Maximum current into VDD pin ..............................................................................................................................125 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... �20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. �20 mA

Maximum output current sunk by any output pin ....................................................................................................25 mA

Maximum output current sourced by any output pin ...............................................................................................25 mA

Note: Power dissipation is calculated as follows:

PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL)

NOTE: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested

or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., out-

side specified power supply range) and therefore outside the warranted range.

� 2007 Microchip Technology Inc. DS21952B-page 27

MCP23017/MCP23S17

2.1 DC Characteristics

DC Characteristics Operating Conditions (unless otherwise indicated):

1.8V VDD 5.5V at -40�C TA +85�C (I-Temp)

4.5V VDD 5.5V at -40�C TA +125�C (E-Temp) (Note 1)

Param Characteristic Sym Min Typ Max Units Conditions

No. (Note 1(

D001 Supply Voltage VDD 1.8 -- 5.5 V

D002 VDD Start Voltage to VPOR -- VSS -- V

Ensure Power-on

Reset

D003 VDD Rise Rate to SVDD 0.05 -- -- V/ms Design guidance only.

Ensure Power-on Not tested.

Reset

D004 Supply Current IDD -- -- 1 mA SCL/SCK = 1 MHz

D005 Standby current IDDS -- -- 1 �A

-- -- 3 �A 4.5V-5.5V @ +125�C

(Note 1)

Input Low Voltage

D030 A0, A1 (TTL buffer) VIL VSS -- 0.15 VDD V

0.2 VDD V

D031 CS, GPIO, SCL/SCK, VSS --

SDA, A2, RESET

(Schmitt Trigger)

Input High Voltage

D040 A0, A1 VIH 0.25 VDD + 0.8 -- VDD V

(TTL buffer)

D041 CS, GPIO, SCL/SCK, 0.8 VDD -- VDD V For entire VDD range

SDA, A2, RESET

(Schmitt Trigger)

Input Leakage Current

D060 I/O port pins IIL -- -- �1 �A VSS VPIN VDD

Output Leakage Current

D065 I/O port pins ILO -- -- �1 �A VSS VPIN VDD

D070 GPIO weak pull-up IPU 40 75 115 �A VDD = 5V, GP Pins = VSS

current �40�C TA +85�C

Output Low-Voltage

D080 GPIO VOL -- -- 0.6 V IOL = 8.0 mA, VDD = 4.5V

INT -- -- 0.6 V IOL = 1.6 mA, VDD = 4.5V

SO, SDA -- -- 0.6 V IOL = 3.0 mA, VDD = 1.8V

SDA -- -- 0.8 V IOL = 3.0 mA, VDD = 4.5V

Output High-Voltage

D090 GPIO, INT, SO VOH VDD � 0.7 -- -- V IOH = -3.0 mA, VDD = 4.5V

VDD � 0.7 -- -- IOH = -400 �A, VDD = 1.8V

Capacitive Loading Specs on Output Pins

D101 GPIO, SO, INT CIO -- -- 50 pF

D102 SDA CB -- -- 400 pF

Note 1: This parameter is characterized, not 100% tested.

DS21952B-page 28 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

FIGURE 2-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

VDD

SCL and 1 k Pin

SDA pin 135 pF 50 pF

MCP23017

FIGURE 2-2: RESET AND DEVICE RESET TIMER TIMING

VDD

30 32

RESET

Internal

RESET

Output pin

� 2007 Microchip Technology Inc. DS21952B-page 29

MCP23017/MCP23S17

TABLE 2-1: DEVICE RESET SPECIFICATIONS

AC Characteristics Operating Conditions (unless otherwise indicated):

1.8V VDD 5.5V at -40�C TA +85�C (I-Temp)

4.5V VDD 5.5V at -40�C TA +125�C (E-Temp) (Note 1)

Param Characteristic Sym Min Typ(1) Max Units Conditions

No.

30 RESET Pulse Width TRSTL 1 -- -- �s

(Low)

32 Device Active After Reset THLD -- 0 -- ns VDD = 5.0V

high

34 Output High-Impedance TIOZ -- -- 1 �s

From RESET Low

Note 1: This parameter is characterized, not 100% tested.

FIGURE 2-3: I2CTM BUS START/STOP BITS TIMING

SCL 91 93

SDA 90 92

Start Stop

Condition Condition

FIGURE 2-4: I2CTM BUS DATA TIMING 102

SCL 103 100

SDA 110

In 101

SDA

Out 90 106

91 107

109 109

DS21952B-page 30 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

TABLE 2-2: I2CTM BUS DATA REQUIREMENTS

I2CTM AC Characteristics Operating Conditions (unless otherwise indicated):

1.8V VDD 5.5V at -40�C TA +85�C (I-Temp)

4.5V VDD 5.5V at -40�C TA +125�C (E-Temp) (Note 1)

RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF

Param Characteristic Sym Min Typ Max Units Conditions

No.

100 Clock High Time: THIGH

100 kHz mode 4.0 -- -- �s 1.8V�5.5V (I-Temp)

400 kHz mode 0.6 -- -- �s 2.7V�5.5V (I-Temp)

1.7 MHz mode 0.12 -- -- �s 4.5V�5.5V (E-Temp)

101 Clock Low Time: TLOW

100 kHz mode 4.7 -- -- �s 1.8V�5.5V (I-Temp)

400 kHz mode 1.3 -- -- �s 2.7V�5.5V (I-Temp)

1.7 MHz mode 0.32 -- -- �s 4.5V�5.5V (E-Temp)

102 SDA and SCL Rise Time: TR

100 kHz mode

400 kHz mode (Note 1) -- -- 1000 ns 1.8V�5.5V (I-Temp)

20 + 0.1 CB(2) -- 300 ns 2.7V�5.5V (I-Temp)

1.7 MHz mode 20 -- 160 ns 4.5V�5.5V (E-Temp)

103 SDA and SCL Fall Time: TF

100 kHz mode

400 kHz mode (Note 1) -- -- 300 ns 1.8V�5.5V (I-Temp)

20 + 0.1 CB(2) -- 300 ns 2.7V�5.5V (I-Temp)

1.7 MHz mode 20 -- 80 ns 4.5V�5.5V (E-Temp)

90 START Condition Setup Time: TSU:STA

100 kHz mode 4.7 -- -- �s 1.8V�5.5V (I-Temp)

400 kHz mode 0.6 -- -- �s 2.7V�5.5V (I-Temp)

1.7 MHz mode 0.16 -- -- �s 4.5V�5.5V (E-Temp)

91 START Condition Hold Time: THD:STA

100 kHz mode 4.0 -- -- �s 1.8V�5.5V (I-Temp)

400 kHz mode 0.6 -- -- �s 2.7V�5.5V (I-Temp)

1.7 MHz mode 0.16 -- -- �s 4.5V�5.5V (E-Temp)

106 Data Input Hold Time: THD:DAT

100 kHz mode 0 -- 3.45 �s 1.8V�5.5V (I-Temp)

400 kHz mode 0 -- 0.9 �s 2.7V�5.5V (I-Temp)

1.7 MHz mode 0 -- 0.15 �s 4.5V�5.5V (E-Temp)

107 Data Input Setup Time: TSU:DAT

100 kHz mode 250 -- -- ns 1.8V�5.5V (I-Temp)

400 kHz mode 100 -- -- ns 2.7V�5.5V (I-Temp)

1.7 MHz mode 0.01 -- -- �s 4.5V�5.5V (E-Temp)

92 Stop Condition Setup Time: TSU:STO

100 kHz mode 4.0 -- -- �s 1.8V�5.5V (I-Temp)

400 kHz mode 0.6 -- -- �s 2.7V�5.5V (I-Temp)

1.7 MHz mode 0.16 -- -- �s 4.5V�5.5V (E-Temp)

Note 1: This parameter is characterized, not 100% tested.

2: CB is specified to be from 10 to 400 pF.

� 2007 Microchip Technology Inc. DS21952B-page 31

MCP23017/MCP23S17

TABLE 2-2: I2CTM BUS DATA REQUIREMENTS (CONTINUED)

I2CTM AC Characteristics Operating Conditions (unless otherwise indicated):

1.8V VDD 5.5V at -40�C TA +85�C (I-Temp)

4.5V VDD 5.5V at -40�C TA +125�C (E-Temp) (Note 1)

RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF

Param Characteristic Sym Min Typ Max Units Conditions

No.

109 Output Valid From Clock: TAA

100 kHz mode -- -- 3.45 �s 1.8V�5.5V (I-Temp)

-- 0.9 �s 2.7V�5.5V (I-Temp)

400 kHz mode -- -- 0.18 �s 4.5V�5.5V (E-Temp)

1.7 MHz mode -- -- -- �s 1.8V�5.5V (I-Temp)

-- -- �s 2.7V�5.5V (I-Temp)

110 Bus Free Time: TBUF -- N/A �s 4.5V � 5.5V (E-Temp)

100 kHz mode 4.7 -- 400 pF Note 1

-- 100 pF Note 1

400 kHz mode 1.3

1.7 MHz mode N/A

Bus Capacitive Loading: CB

100 kHz and 400 kHz --

1.7 MHz --

Input Filter Spike Suppression TSP

(SDA and SCL)

100 kHz and 400 kHz -- -- 50 ns

-- 10 ns Spike suppression off

1.7 MHz --

Note 1: This parameter is characterized, not 100% tested.

2: CB is specified to be from 10 to 400 pF.

FIGURE 2-5: SPI INPUT TIMING

CS 3

1 6 11

Mode 1,1 10

SCK Mode 0,0 7 2

4 5

MSB in LSB in

SO High-Impedance

DS21952B-page 32 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

FIGURE 2-6: SPI OUTPUT TIMING

CS 8 9 2

SCK Mode 1,1

12 13 Mode 0,0

SO MSB out Don't Care

SI 14

LSB out

TABLE 2-3: SPI INTERFACE AC CHARACTERISTICS

SPI Interface AC Characteristics Operating Conditions (unless otherwise indicated):

1.8V VDD 5.5V at -40�C TA +85�C (I-Temp)

4.5V VDD 5.5V at -40�C TA +125�C (E-Temp) (Note 1)

Param Characteristic Sym Min Typ Max Units Conditions

No.

Clock Frequency FCLK -- -- 5 MHz 1.8V�5.5V (I-Temp)

-- -- 10 MHz 2.7V�5.5V (I-Temp)

-- -- 10 MHz 4.5V�5.5V (E-Temp)

1 CS Setup Time TCSS 50 -- -- ns

2 CS Hold Time TCSH 100 -- -- ns 1.8V�5.5V (I-Temp)

50 -- -- ns 2.7V�5.5V (I-Temp)

50 -- -- ns 4.5V�5.5V (E-Temp)

3 CS Disable Time TCSD 100 -- -- ns 1.8V�5.5V (I-Temp)

50 -- -- ns 2.7V�5.5V (I-Temp)

50 -- -- ns 4.5V�5.5V (E-Temp)

4 Data Setup Time TSU 20 -- -- ns 1.8V�5.5V (I-Temp)

10 -- -- ns 2.7V�5.5V (I-Temp)

10 -- -- ns 4.5V�5.5V (E-Temp)

5 Data Hold Time THD 20 -- -- ns 1.8V�5.5V (I-Temp)

10 -- -- ns 2.7V�5.5V (I-Temp)

10 -- -- ns 4.5V�5.5V (E-Temp)

6 CLK Rise Time TR ---- 2 �s Note 1

7 CLK Fall Time TF ---- 2 �s Note 1

8 Clock High Time THI 90 -- -- ns 1.8V�5.5V (I-Temp)

45 -- -- ns 2.7V�5.5V (I-Temp)

45 -- -- ns 4.5V�5.5V (E-Temp)

Note 1: This parameter is characterized, not 100% tested.

� 2007 Microchip Technology Inc. DS21952B-page 33

MCP23017/MCP23S17

TABLE 2-3: SPI INTERFACE AC CHARACTERISTICS (CONTINUED)

SPI Interface AC Characteristics Operating Conditions (unless otherwise indicated):

1.8V VDD 5.5V at -40�C TA +85�C (I-Temp)

4.5V VDD 5.5V at -40�C TA +125�C (E-Temp) (Note 1)

Param Characteristic Sym Min Typ Max Units Conditions

No.

9 Clock Low Time TLO 90 -- -- ns 1.8V�5.5V (I-Temp)

45 -- -- ns 2.7V�5.5V (I-Temp)

45 -- -- ns 4.5V�5.5V (E-Temp)

10 Clock Delay Time TCLD 50 -- -- ns

11 Clock Enable Time TCLE 50 -- -- ns

12 Output Valid from Clock Low TV -- -- 90 ns 1.8V�5.5V (I-Temp)

-- -- 45 ns 2.7V�5.5V (I-Temp)

-- -- 45 ns 4.5V�5.5V (E-Temp)

13 Output Hold Time THO 0 -- -- ns

14 Output Disable Time TDIS -- -- 100 ns

Note 1: This parameter is characterized, not 100% tested.

FIGURE 2-7: GPIO AND INT TIMING

SCL/SCK D1 D0

SDA/SI

In LSb of data byte zero

GPn during a write or read

Output

command, depending

on parameter 50

INT

Pin INT Pin Active 51

Inactive

GPn 53

Input 52

Loaded

DS21952B-page 34 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

TABLE 2-4: GP AND INT PINS

AC Characteristics Operating Conditions (unless otherwise indicated):

1.8V VDD 5.5V at -40�C TA +85�C (I-Temp)

4.5V VDD 5.5V at -40�C TA +125�C (E-Temp) (Note 1)

Param Characteristic Sym Min Typ Max Units Conditions

No.

500 ns

50 Serial Data to Output Valid TGPOV -- -- 600 ns

450 ns

51 Interrupt Pin Disable Time TINTD -- --

52 GP Input Change to TGPIV -- --

53 IOC Event to INT Active TGPINT -- -- 600 ns

150 ns Note 1

Glitch Filter on GP Pins TGLITCH -- --

Note 1: This parameter is characterized, not 100% tested

� 2007 Microchip Technology Inc. DS21952B-page 35

MCP23017/MCP23S17

NOTES:

DS21952B-page 36 � 2007 Microchip Technology Inc.

3.0 PACKAGING INFORMATION MCP23017/MCP23S17

3.1 Package Marking Information Example:

MCP23017-E/SP^e^3

28-Lead PDIP (Skinny DIP) 0648256

XXXXXXXXXXXXXXXXX Example:

XXXXXXXXXXXXXXXXX

23017

YYWWNN E/ML^e^3

0648256

28-Lead QFN Example:

XXXXXXXX MCP23017-E/SO^e^3

XXXXXXXX 0648256

YYWWNNN

Example:

28-Lead SOIC MCP23017

E/SS^e^3

XXXXXXXXXXXXXXXXX 0648256

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead SSOP

XXXXXXXXXXXX

YYWWNNN

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week `01')

NNN Alphanumeric traceability code

e3 Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator ( e3 )

* can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

� 2007 Microchip Technology Inc. DS21952B-page 37

MCP23017/MCP23S17

28-Lead Skinny Plastic Dual In-Line (SP) � 300 mil Body [SPDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N E1

NOTE 1

1 23

A A2 E

A1 b1 c

e eB

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e .100 BSC

Top to Seating Plane A � � .200

Molded Package Thickness A2 .120 .135 .150

Base to Seating Plane A1 .015 � �

Shoulder to Shoulder Width E .290 .310 .335

Molded Package Width E1 .240 .285 .295

Overall Length D 1.345 1.365 1.400

Tip to Seating Plane L .110 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .050 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing � eB � � .430

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. � Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-070B

DS21952B-page 38 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

28-Lead Plastic Quad Flat, No Lead Package (ML) � 6x6 mm Body [QFN]

with 0.55 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D EXPOSED D2

PAD

E E2 e

2 2

1 1 K

N NOTE 1 N

TOP VIEW

BOTTOM VIEW

A3 A1

Units MILLIMETERS

Dimension Limits

MIN NOM MAX

Number of Pins N 28

Pitch

Overall Height e 0.65 BSC

A 0.80 0.90 1.00

Standoff A1 0.00 0.02 0.05

Contact Thickness

Overall Width A3 0.20 REF

Exposed Pad Width

E 6.00 BSC

E2 3.65 3.70 4.20

Overall Length D 6.00 BSC

Exposed Pad Length

Contact Width D2 3.65 3.70 4.20

b 0.23 0.30 0.35

Contact Length L 0.50 0.55 0.70

Contact-to-Exposed Pad K 0.20 � �

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-105B

� 2007 Microchip Technology Inc. DS21952B-page 39

MCP23017/MCP23S17

28-Lead Plastic Small Outline (SO) � Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

NOTE 1 E

123

b e

A A2

A1 L1

Units MILLMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e 1.27 BSC

Overall Height A � � 2.65

Molded Package Thickness A2 2.05 � �

Standoff � A1 0.10 � 0.30

Overall Width E 10.30 BSC

Molded Package Width E1 7.50 BSC

Overall Length D 17.90 BSC

Chamfer (optional) h 0.25 � 0.75

Foot Length L 0.40 � 1.27

Footprint L1 1.40 REF

Foot Angle Top 0� � 8�

Lead Thickness c 0.18 � 0.33

Lead Width b 0.31 � 0.51

Mold Draft Angle Top 5� � 15�

Mold Draft Angle Bottom 5� � 15�

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. � Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-052B

DS21952B-page 40 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

28-Lead Plastic Shrink Small Outline (SS) � 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

NOTE 1 b

A A2

L1 L

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e 0.65 BSC

Overall Height A � � 2.00

Molded Package Thickness A2 1.65 1.75 1.85

Standoff A1 0.05 � �

Overall Width E 7.40 7.80 8.20

Molded Package Width E1 5.00 5.30 5.60

Overall Length D 9.90 10.20 10.50

Foot Length L 0.55 0.75 0.95

Footprint L1 1.25 REF

Lead Thickness c 0.09 � 0.25

Foot Angle 0� 4� 8�

Lead Width b 0.22 � 0.38

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-073B

� 2007 Microchip Technology Inc. DS21952B-page 41

MCP23017/MCP23S17

NOTES:

DS21952B-page 42 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

APPENDIX A: REVISION HISTORY

Revision B (February 2007)

1. Changed Byte and Sequential Read in

Figure 1-1 from "R" to "W".

2. Table 2-4, Param No. 51 and 53: Changed from

450 to 600 and 500 to 600, respecively.

3. Added disclaimers to package outline drawings.

4. Updated package outline drawings.

Revision A (June 2005)

� Original Release of this Document.

� 2007 Microchip Technology Inc. DS21952B-page 39

MCP23017/MCP23S17

NOTES:

DS21952B-page 40 � 2007 Microchip Technology Inc.

MCP23017/MCP23S17

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. � X /XX Examples:

Device Temperature Package a) MCP23017-E/SP: Extended Temp.,

Range 28LD PDIP package.

Device MCP23017: 16-Bit I/O Expander w/I2CTM Interface b) MCP23017-E/SO: Extended Temp.,

MCP23017T: 16-Bit I/O Expander w/I2C Interface 28LD SOIC package.

(Tape and Reel)

MCP23S17: 16-Bit I/O Expander w/SPI Interface c) MCP23017T-E/SO: Tape and Reel,

MCP23S17T: 16-Bit I/O Expander w/SPI Interface Extended Temp.,

(Tape and Reel) 28LD SOIC package.

Temperature E = -40�C to +125�C (Extended) d) MCP23017-E/SS: Extended Temp.,

Range 28LD SSOP package.

Package ML = Plastic Quad, Flat No Leads (QFN), 28-lead e) MCP23017T-E/SS: Tape and Reel,

SP = Plastic DIP (300 mil Body), 28-Lead Extended Temp.,

SO = Plastic SOIC (300 mil Body), 28-Lead 28LD SSOP package.

SS = SSOP, (209 mil Body, 5.30 mm), 28-Lead

a) MCP23S17-E/SP: Extended Temp.,

28LD PDIP package.

b) MCP23S17-E/SO: Extended Temp.,

28LD SOIC package.

c) MCP23S17T-E/SO: Tape and Reel,

Extended Temp.,

28LD SOIC package.

d) MCP23S17-E/SS: Extended Temp.,

28LD SSOP package.

e) MCP23S17T-E/SS: Tape and Reel,

Extended Temp.,

28LD SSOP package.

� 2007 Microchip Technology Inc. DS21952B-page 41

MCP23017/MCP23S17

NOTES:

DS21952B-page 42 � 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

� Microchip products meet the specification contained in their particular Microchip Data Sheet.

� Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

� There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

� Microchip is willing to work with the customer who is concerned about the integrity of their code.

� Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, Accuron,

ensure that your application meets with your specifications. dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

MICROCHIP MAKES NO REPRESENTATIONS OR PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and

WARRANTIES OF ANY KIND WHETHER EXPRESS OR SmartShunt are registered trademarks of Microchip

IMPLIED, WRITTEN OR ORAL, STATUTORY OR Technology Incorporated in the U.S.A. and other countries.

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION, AmpLab, FilterLab, Linear Active Thermistor, Migratable

QUALITY, PERFORMANCE, MERCHANTABILITY OR Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor

FITNESS FOR PURPOSE. Microchip disclaims all liability and The Embedded Control Solutions Company are

arising from this information and its use. Use of Microchip registered trademarks of Microchip Technology Incorporated

devices in life support and/or safety applications is entirely at in the U.S.A.

the buyer's risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims, Analog-for-the-Digital Age, Application Maestro, CodeGuard,

suits, or expenses resulting from such use. No licenses are dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

intellectual property rights. In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

� 2007, Microchip Technology Incorporated, Printed in the

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company's quality system processes and procedures are for its PIC�

MCUs and dsPIC� DSCs, KEELOQ� code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip's quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

� 2007 Microchip Technology Inc. DS21952B-page 43

WORLDWIDE SALES AND SERVICE

AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE

Corporate Office Asia Pacific Office India - Bangalore Austria - Wels

2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-4182-8400 Tel: 43-7242-2244-39

Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-4182-8422 Fax: 43-7242-2244-393

Tel: 480-792-7200 Habour City, Kowloon Denmark - Copenhagen

Fax: 480-792-7277 Hong Kong India - New Delhi Tel: 45-4450-2828

Technical Support: Tel: 852-2401-1200 Tel: 91-11-4160-8631 Fax: 45-4485-2829

http://support.microchip.com Fax: 852-2401-3431 Fax: 91-11-4160-8632

Web Address: France - Paris

www.microchip.com Australia - Sydney India - Pune Tel: 33-1-69-53-63-20

Tel: 61-2-9868-6733 Tel: 91-20-2566-1512 Fax: 33-1-69-30-90-79

Atlanta Fax: 61-2-9868-6755 Fax: 91-20-2566-1513

Duluth, GA Germany - Munich

Tel: 678-957-9614 China - Beijing Japan - Yokohama Tel: 49-89-627-144-0

Fax: 678-957-1455 Tel: 86-10-8528-2100 Tel: 81-45-471- 6166 Fax: 49-89-627-144-44

Fax: 86-10-8528-2104 Fax: 81-45-471-6122

Boston Italy - Milan

Westborough, MA China - Chengdu Korea - Gumi Tel: 39-0331-742611

Tel: 774-760-0087 Tel: 86-28-8665-5511 Tel: 82-54-473-4301 Fax: 39-0331-466781

Fax: 774-760-0088 Fax: 86-28-8665-7889 Fax: 82-54-473-4302

Netherlands - Drunen

Chicago China - Fuzhou Korea - Seoul Tel: 31-416-690399

Itasca, IL Tel: 86-591-8750-3506 Tel: 82-2-554-7200 Fax: 31-416-690340

Tel: 630-285-0071 Fax: 86-591-8750-3521 Fax: 82-2-558-5932 or

Fax: 630-285-0075 82-2-558-5934 Spain - Madrid

China - Hong Kong SAR Tel: 34-91-708-08-90

Dallas Tel: 852-2401-1200 Malaysia - Penang Fax: 34-91-708-08-91

Addison, TX Fax: 852-2401-3431 Tel: 60-4-646-8870

Tel: 972-818-7423 Fax: 60-4-646-5086 UK - Wokingham

Fax: 972-818-2924 China - Qingdao Tel: 44-118-921-5869

Tel: 86-532-8502-7355 Philippines - Manila Fax: 44-118-921-5820

Detroit Fax: 86-532-8502-7205 Tel: 63-2-634-9065

Farmington Hills, MI Fax: 63-2-634-9069

Tel: 248-538-2250 China - Shanghai

Fax: 248-538-2260 Tel: 86-21-5407-5533 Singapore

Fax: 86-21-5407-5066 Tel: 65-6334-8870

Kokomo Fax: 65-6334-8850

Kokomo, IN China - Shenyang

Tel: 765-864-8360 Tel: 86-24-2334-2829 Taiwan - Hsin Chu

Fax: 765-864-8387 Fax: 86-24-2334-2393 Tel: 886-3-572-9526

Fax: 886-3-572-6459

Los Angeles China - Shenzhen

Mission Viejo, CA Tel: 86-755-8203-2660 Taiwan - Kaohsiung

Tel: 949-462-9523 Fax: 86-755-8203-1760 Tel: 886-7-536-4818

Fax: 949-462-9608 Fax: 886-7-536-4803

China - Shunde

Santa Clara Tel: 86-757-2839-5507 Taiwan - Taipei

Santa Clara, CA Fax: 86-757-2839-5571 Tel: 886-2-2500-6610

Tel: 408-961-6444 Fax: 886-2-2508-0102

Fax: 408-961-6445 China - Wuhan

Tel: 86-27-5980-5300 Thailand - Bangkok

Toronto Fax: 86-27-5980-5118 Tel: 66-2-694-1351

Mississauga, Ontario, Fax: 66-2-694-1350

Canada China - Xian

Tel: 905-673-0699 Tel: 86-29-8833-7250

Fax: 905-673-6509 Fax: 86-29-8833-7256

DS21952B-page 44 12/08/06

� 2007 Microchip Technology Inc.

This datasheet has been downloaded from:

www.EEworld.com.cn

Free Download

Daily Updated Database

100% Free Datasheet Search Site

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All Datasheets Cannot Be Modified Without Permission

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